Typically, defects are generated when novel materials, for example III-V materials are grown on a silicon (“Si”) substrate due to lattice mismatch. These defects can reduce the mobility of carriers (e.g., electrons, holes, or both) in the III-V materials.
Due to the defects generation, integration of the III-V material based devices, germanium based devices, or other lattice mismatched materials based devices onto a silicon substrate for Complementary Metal-Oxide Semiconductor (“CMOS”) systems is a big challenge.
Currently, a selective area epitaxy is used to form MOS devices on a silicon substrate. Generally, selective area epitaxy is referred to the local growth of an epitaxial layer through a patterned dielectric mask deposited on a semiconductor substrate. Due to lattice mismatch, the defects are generated when the III-V based devices are locally grown on a patterned silicon substrate. Currently there is no state of art solution to integrate n-type and p-type III-V materials based MOS devices on to a silicon substrate.